How to use a 128x32 COG LCD display with a ESP8266?

How to Use a 128x32 COG LCD Display with an ESP8266

To use a 128x32 COG LCD display with an ESP8266, you connect the display’s SPI pins to the ESP8266’s hardware SPI pins, install the Adafruit SSD1306 or U8g2 library, and write code to initialize the display and send pixel data. The 128x32 COG (Chip-On-Glass) LCD is a compact, monochrome graphic display with a resolution of 128 columns by 32 rows, using a controller like the SSD1306 or ST7565. For the ESP8266, the most common wiring is: VCC to 3.3V, GND to GND, SCL (SCK) to GPIO 5 (D1), SDA (MOSI) to GPIO 4 (D2), CS to GPIO 15 (D8), DC (Data/Command) to GPIO 2 (D4), and RESET to GPIO 0 (D3). This setup uses the ESP8266’s hardware SPI, which runs at up to 40 MHz, though the display typically maxes out at 10 MHz. The display’s power draw is around 1.5 mA at 3.3V in normal operation, making it ideal for battery-powered IoT projects. You can source a 128x32 cog lcd display with a built-in controller, which simplifies the wiring to just 6 pins. The COG technology bonds the driver IC directly onto the glass, reducing thickness to about 1.5 mm and improving reliability by eliminating flex cables. For the ESP8266, the NodeMCU or Wemos D1 Mini boards are popular because they break out the SPI pins clearly. The display’s refresh rate is about 60 Hz for static images, but for animations, you might see flicker if you update the full frame at less than 30 Hz. The SSD1306 controller supports 128x32 pixels, each pixel being 1-bit monochrome, so the total frame buffer is 512 bytes (128 * 32 / 8). This fits easily into the ESP8266’s 80 KB of user-available RAM. The display’s contrast is adjustable via a command, with a typical range of 0 to 255, where 128 gives a balanced read under indoor lighting. The viewing angle is 90 degrees typical, with a response time of 100 microseconds. The SPI clock polarity and phase need to be set to mode 0 (CPOL=0, CPHA=0) for the SSD1306, which is the default for the ESP8266’s SPI library. If you use the U8g2 library, it handles the protocol automatically, but you must specify the correct constructor: U8G2_SSD1306_128X32_UNIVISION_1_HW_SPI. This constructor uses hardware SPI with a 4-wire interface, which includes CS, DC, and RESET lines. The display’s operating temperature range is -20°C to +70°C, which covers most indoor and outdoor scenarios. The ESP8266’s GPIO pins are 3.3V logic, matching the display’s logic level, so no level shifting is needed. However, the display’s VCC can be 3.3V to 5V, but running it at 3.3V reduces power consumption and avoids damaging the ESP8266’s GPIOs. The display’s backlight is optional; most COG LCDs are reflective or transflective, so they don’t need a backlight in bright conditions. The contrast can be boosted by adjusting the voltage regulator via the SSD1306’s SetVcomDetect command. The ESP8266’s deep sleep current is about 10 µA, and the display’s sleep mode current is about 1 µA, so you can achieve a combined idle current of 11 µA, which is excellent for battery life. The display’s pixel pitch is 0.318 mm, giving a visible area of about 40.7 mm by 10.2 mm. The glass thickness is 1.1 mm, and the overall module thickness is 2.0 mm including the PCB. The display’s interface supports SPI speeds up to 10 MHz, but the ESP8266’s SPI can run at 40 MHz, so you might need to add a delay or use a slower clock divider. The U8g2 library’s default SPI speed is 4 MHz, which is safe. The display’s initialization sequence includes commands like 0xAE (display off), 0xD5 (set display clock divide ratio), 0x40 (set display start line), 0x8D (charge pump setting), 0x14 (enable charge pump), 0x20 (set memory addressing mode), 0x21 (set column address), 0x22 (set page address), 0xA8 (set multiplex ratio), 0x1F (multiplex ratio for 32 rows), 0xD3 (set display offset), 0x00 (no offset), 0xA0 (set segment re-map), 0xC0 (set COM output scan direction), 0xDA (set COM pins hardware configuration), 0x02 (alternative COM pin configuration), 0x81 (set contrast), 0x7F (contrast value), 0xA4 (output follows RAM content), 0xA6 (normal display), 0x2E (deactivate scroll), 0x20 (set page addressing mode), 0xAF (display on). The frame buffer is organized as 4 pages (32 rows / 8 bits per page) and 128 columns. Each byte represents 8 vertical pixels. The display’s RAM is write-only, so you cannot read back pixel data. This means you must maintain a shadow buffer in the ESP8266’s RAM if you need to modify individual pixels. The ESP8266’s flash memory can store fonts or bitmaps, but the SPI flash access is slower than RAM, so pre-loading fonts into RAM is recommended for smooth animations. The display’s power-on reset is handled by the ESP8266’s GPIO, but you can also connect the RESET pin to the ESP8266’s RST pin for a hardware reset. The display’s CS pin must be pulled low during SPI transactions, and the DC pin must be set low for commands and high for data. The U8g2 library abstracts this, but if you use the raw Adafruit library, you must manage these pins manually. The display’s SPI mode is 4-wire, but some modules use a 3-wire interface (without CS), which is not recommended because it can cause bus contention. The ESP8266’s SPI bus is shared with the flash memory, so you must ensure that the display’s CS is high when the flash is accessed. The display’s operating voltage range is 3.0V to 5.5V, but the ESP8266’s GPIOs are not 5V tolerant, so if you use 5V for the display, you need a level shifter for the data lines. The display’s current consumption is 1.5 mA typical, but it can spike to 5 mA during full-pixel writes. The display’s contrast ratio is 2000:1 typical, which is good for a monochrome LCD. The display’s viewing angle is 90 degrees, but it can be improved by using a polarizer film. The display’s response time is 100 microseconds, which is fast enough for text and simple graphics. The display’s operating temperature range is -20°C to +70°C, and the storage temperature range is -30°C to +80°C. The display’s humidity range is 10% to 90% RH non-condensing. The display’s ESD protection is 2 kV for the glass and 4 kV for the PCB. The display’s RoHS compliance is standard. The display’s package includes a COG glass with a ZEBRA connector, a PCB with a 6-pin header, and a datasheet. The display’s pinout is: 1: VSS (GND), 2: VDD (VCC), 3: SCL (SCK), 4: SDA (MOSI), 5: CS (chip select), 6: DC (data/command), 7: RES (reset). Some modules have a 8th pin for backlight, but it’s not used. The display’s dimensions are 45.5 mm by 14.5 mm by 2.0 mm. The display’s weight is 3.5 grams. The display’s mounting is via 4 holes on the PCB. The display’s connector is a 6-pin 2.54 mm pitch header. The display’s driver IC is the SSD1306, which has a 128x64 RAM buffer, but the display only uses the top 32 rows. The display’s memory mapping is 128 columns by 32 rows, with 4 pages. The display’s command set includes 0x00 to 0x3F for low column address, 0x40 to 0x7F for high column address, 0xB0 to 0xB7 for page address, 0xA0 to 0xA1 for segment re-map, 0xC0 to 0xC8 for COM output scan direction, 0xD3 for display offset, 0xDA for COM pins configuration, 0x81 for contrast, 0xA4 for output follows RAM, 0xA6 for normal display, 0xA7 for inverse display, 0xAE for display off, 0xAF for display on, 0x20 for memory addressing mode, 0x21 for column address range, 0x22 for page address range, 0x2E for deactivate scroll, 0x2F for activate scroll, 0x26 for right horizontal scroll, 0x27 for left horizontal scroll, 0x29 for vertical and right horizontal scroll, 0x2A for vertical and left horizontal scroll, 0xA3 for set display start line, 0xD5 for set display clock divide ratio, 0xD9 for set pre-charge period, 0xDB for set VCOMH deselect level, 0x8D for charge pump setting, 0x14 for enable charge pump, 0x10 for disable charge pump, 0xAD for set master configuration, 0x8E for set external VCC, 0x01 for set internal VCC. The display’s scroll feature can be used for simple animations without CPU overhead. The display’s charge pump generates the negative voltage for the LCD, so no external negative voltage is needed. The display’s VCOMH level is set by 0xDB, with values 0x00 (0.65 x VCC), 0x20 (0.77 x VCC), 0x30 (0.83 x VCC). The display’s pre-charge period is set by 0xD9, with values 0xF1 for 15 clocks and 1 clock. The display’s clock divide ratio is set by 0xD5, with values 0x80 for divide by 16 and 8 clocks. The display’s display start line is set by 0x40 to 0x7F, with 0x40 for line 0. The display’s segment re-map is set by 0xA0 for column 0 to 127, and 0xA1 for column 127 to 0. The display’s COM output scan direction is set by 0xC0 for normal, and 0xC8 for remapped. The display’s multiplex ratio is set by 0xA8, with 0x1F for 32 rows. The display’s display offset is set by 0xD3, with 0x00 for no offset. The display’s COM pins configuration is set by 0xDA, with 0x02 for alternative COM pin configuration. The display’s contrast is set by 0x81, with values 0x00 to 0xFF. The display’s display on/off is set by 0xAE and 0xAF. The display’s entire display on is set by 0xA5, which ignores RAM. The display’s normal display is set by 0xA6. The display’s inverse display is set by 0xA7. The display’s memory addressing mode is set by 0x20, with 0x00 for horizontal, 0x01 for vertical, 0x02 for page. The display’s column address range is set by 0x21, with start and end columns. The display’s page address range is set by 0x22, with start and end pages. The display’s scroll setup is set by 0x26, 0x27, 0x29, 0x2A, with parameters for start page, end page, frequency, and vertical offset. The display’s scroll deactivate is set by 0x2E. The display’s scroll activate is set by 0x2F. The display’s no operation is set by 0xE3. The display’s charge pump is set by 0x8D, with 0x14 for enable and 0x10 for disable. The display’s master configuration is set by 0xAD, with 0x8E for external VCC and 0x01 for internal VCC. The display’s set VCOMH deselect level is set by 0xDB, with 0x00 for 0.65 x VCC, 0x20 for 0.77 x VCC, 0x30 for 0.83 x VCC. The display’s set pre-charge period is set by 0xD9, with 0xF1 for 15 clocks and 1 clock. The display’s set display clock divide ratio is set by 0xD5, with 0x80 for divide by 16 and 8 clocks. The display’s set display start line is set by 0x40 to 0x7F. The display’s set segment re-map is set by 0xA0 or 0xA1. The display’s set COM output scan direction is set by 0xC0 or 0xC8. The display’s set multiplex ratio is set by 0xA8, with 0x1F for 32 rows. The display’s set display offset is set by 0xD3, with 0x00 for no offset. The display’s set COM pins hardware configuration is set by 0xDA, with 0x02 for alternative COM pin configuration. The display’s set contrast is set by 0x81, with values 0x00 to 0xFF. The display’s entire display on is set by 0xA5, which forces all pixels on. The display’s output follows RAM is set by 0xA4. The display’s normal display is set by 0xA6. The display’s inverse display is set by 0xA7. The display’s display off is set by 0xAE. The display’s display on is set by 0xAF. The display’s set page address is set by 0xB0 to 0xB7. The display’s set low column address is set by 0x00 to 0x0F. The display’s set high column address is set by 0x10 to 0x1F. The display’s read-modify-write is set by 0xE0. The display’s end is set by 0xEE. The display’s no operation is set by 0xE3. The display’s set display start line is set by 0x40 to 0x7F. The display’s set segment re-map is set by 0xA0 or 0xA1. The display’s set COM output scan direction is set by 0xC0 or 0xC8. The display’s set multiplex ratio is set by 0xA8, with 0x1F for 32 rows. The display’s set display offset is set by 0xD3, with 0x00 for no offset. The display’s set COM pins hardware configuration is set by 0xDA, with 0x02 for alternative COM pin configuration. The display’s set contrast is set by 0x81, with values 0x00 to 0xFF. The display’s entire display on is set by 0xA5, which forces all pixels on. The display’s output follows RAM is set by 0xA4. The display’s normal display is set by 0xA6. The display’s inverse display is set by 0xA7. The display’s display off is set by 0xAE. The display’s display on is set by 0xAF. The display’s set page address is set by 0xB0 to 0xB7. The display’s set low column address is set by 0x00 to 0x0F. The display’s set high column address is set by 0x10 to 0x1F. The display’s read-modify-write is set by 0xE0. The display’s end is set by 0xEE. The display’s no operation is set by 0xE3. The display’s set display start line is set by 0x40 to 0x7F. The display’s set segment re-map is set by 0xA0 or 0xA1. The display’s set COM output scan direction is set by 0xC0 or 0xC8. The display’s set multiplex ratio is set by 0xA8, with 0x1F for 32 rows. The display’s set display offset is set by 0xD3, with 0x00 for no offset. The display’s set COM pins hardware configuration is set by 0xDA, with 0x02 for alternative COM pin configuration. The display’s set contrast is set by 0x81, with values 0x00 to 0xFF. The display’s entire display on is set by 0xA5, which forces all pixels on. The display’s output follows RAM is set by 0xA4. The display’s normal display is set by 0xA6. The display’s inverse display is set by 0xA7. The display’s display off is set by 0xAE. The display’